1. Field of the Invention
This invention generally relates to semiconductors and methods for fabricating thereof, and more particularly, to a technique that has the ability of improving a product yield ratio without degrading operating characteristic of a flash memory cell.
2. Description of the Related Art
Flash memories are a type of electrically rewritable ROM, and are semiconductor devices widely used for mobile telephones, digital steel cameras, or communications networking devices.
Each of the flash memories includes a floating gate provided on a tunnel oxide film and a control gate applying bias to the floating gate. Information is written and erased by injecting or extracting an electron into or from the floating gate via the tunnel oxide film according to the bias applied to the floating gate. Here, a dielectric film is formed on an outer circumference of the floating gate of each cell, serving as a quantum-mechanical energy barrier, so that the injected electron may not be leaked out of the floating gate.
However, as the dielectric film is thinner, there is a higher possibility that the electron that has obtained energy leaps over the energy barrier to the outside of the floating gate. This is the reason the dielectric film is generally composed of an ONO film (a three-layer laminated film of oxide film/nitride film/oxide film) or an ON film (a two-layer laminated film of oxide film/nitride film), both of which have a high dielectric constant (as disclosed in Japanese Patent application Publication No. 2004-193226).
FIGS. 1A through 1D are schematic sectional views of a single memory illustrating a conventional manufacturing process of the flash memory. FIGS. 2A and 2B are schematic plan views of a part of the flash memory in the manufacturing process to describe the schematic sectional views of FIGS. 1A through 1D. FIGS. 1A through 1D are the schematic views taken along a line A-A shown in FIGS. 2A and 2B.
In the above-mentioned figures, a reference numeral 100 represents a semiconductor substrate of silicon or the like, a reference numeral 101 represents a tunnel oxide film, a reference numeral 102 represents a shallow trench isolation (STI), a reference numeral 103 represents polysilicon to be formed into the floating gate, a reference numeral 104 represents a photoresist to serve as a mask for etching, a reference numeral 105 represents an ONO film, and a reference numeral 106 represents an etching residue of the ONO film as will be described later. In addition, a reference numeral 107 is a mask for forming a control gate (control gate mask), a reference numeral 108 represents a floating gate, a reference numeral 109 represents a control gate, and a reference numeral 110 is an active region.
As shown in FIG. 2A, the STI (102) is provided to extend in stripes in parallel with an extending direction of the control gate mask 107, and the polysilicon 103, which will be formed into the floating gate, extends in the same direction as the STI does in stripes in a region sandwiched by two stripes of the STI. Referring to FIGS. 1A through 1D, the thin tunnel oxide film 101 having thickness of 75 to 150 Å is formed on the semiconductor substrate 100. An activating region in each cell is isolated by the STI (102) formed in the semiconductor device 100. The tunnel oxide film 101 and the STI (102) are covered with the polysilicon 103 to be formed into the floating gate, and the photoresist 104, which will serve as a mask to etch a part of the polysilicon 103, is laminated thereon (FIG. 1A). Here, the polysilicon has the thickness of, for example, 300 to 1200 Å. The polysilicon 103 is etched to separate the floating gates 108 in adjacent cells.
After etching is performed with the photoresist 104 serving as a mask, a top surface of the polysilicon 103 provided on the STI (102) is partially etched, and a top surface of the STI (102) is partially exposed. Then, the floating gates 108 in the adjacent cells are separated (FIG. 1B). After the photoresist 104 is removed because the mask is not necessary any longer, the ONO film 105 is laminated on the whole surface of the substrate (FIG. 1C). The ONO film 105 is controlled to have the thickness of 100 to 250 Å in converting the electric characteristic into the oxide film.
Consequently, the polysilicon 103 and the ONO film 105 are removed by dry etching, the polysilicon 103 and the ONO film 105 being provided in regions other than the region to be formed into the control gate (a peripheral region of the cell). However, the ONO film 105 provided on the sidewall of the polysilicon 103 cannot be removed completely, because the ONO film, which has been formed on the sidewall of the polysilicon 103, is relatively thick and has height of 400 to 500 Å (shown as Z′ in FIG. 1C). As a result, a residue of the ONO film 105 is remained (FIG. 1D) on lines shown as dotted lines (FIG. 2B).
As described above, according to the conventional techniques, dry etching for the purpose of separating the control gate cannot remove the whole dielectric film (the ONO film or ON film) formed on the sidewall of the floating gate, resulting in that the dielectric film partially remains as a residue.
The residue of the dielectric film is lifted off in an etching bath in a hydrofluoric acid etching process in a later process, floats as particles in an etchant, and adheres again, lowering the yield of the semiconductor device.
The floating gate, partially remaining on the sidewall of the dielectric film as an etching residue, also causes short-circuiting between the floating gates in the cells adjacent to each other in a direction of the bit line.
In order to solve the above-mentioned problems, the residue of the dielectric film can be reduced by controlling the etching period of the dielectric film that is necessary together with etching in a control gate forming process. However, the etching selectivity of the material of the floating gate to that of the dielectric film is not sufficiently high. This will develop etching of the material of the floating gate too much and lead to over-etching, the over-etching damages the tunnel oxide film, and the device characteristic will be degraded as a result.
The dielectric film formed on the sidewall of the floating gate can be removed by the CMP process. Nevertheless, this method will degrade the degree of the gate coupling, and the device characteristic will be degraded as a result.